The present invention relates to a solid-state image pickup device.
Typically, mainstream cameras used to be those of a film type, but cameras of a digital type have recently become alternatives thereto. Further, image quality improvement in the digital cameras is remarkable, and the latest digital cameras have performance surpassing that of film cameras.
In the digital camera, an object is captured by a lens and focused as an optical image onto a solid-state image pickup device. As this solid-state image pickup device, there are mainly CCD (Charge Coupled Devices) and CMOS (Complementary Metal Oxide Semiconductors) image sensors. From a view point of camera performance improvement, the CMOS image sensors in which a CMOS circuit for image processing can easily be loaded as a peripheral circuit have attracted attention.
The CMOS image sensors include: analog image sensors and digital image sensors. Both of them have advantages and disadvantages, but from a view point of data processing speed, there are high expectations for the detail image sensors. Use of the digital image sensor not only makes it possible to take a moving image of high quality but also enables combination with image processing at a later stage for various applications. For example, it is possible for the camera to automatically determine a shutter chance of an instance at which a ball hits a tennis racket or a close-up photo of a child reaching a goal while running around a playground in an athletic meet and automatically press a shutter only by orienting the camera in the aimed direction.
In the digital image sensor, an analog-to-digital (A/D) converter is provided at each column of a pixel array. For example, Japanese Unexamined Patent Publication No. 2009-130827 discloses a digital image sensor using an A/D converter of an integral type. More specifically, in this document, the pixel array includes a plurality of pixels arrayed in N-number of rows×M-number of columns, and analog pixel signals are outputted to M-number of column signal lines corresponding to the respective columns. A latch circuit is provided in correspondence with each column, and latches, as a digital pixel signal of predetermined bits, a count value for a voltage level of a ramp signal to reach a voltage level of an analog pixel signal read via the corresponding column signal line. The latched digital pixel signal of the predetermined bits is outputted to a control section.
A digital image sensor disclosed in Japanese Unexamined Patent Publication No. 2009-290613 also uses an A/D converter of an integral type. The digital image sensor in this document differs from the digital image sensor in patent document described above in that n-bit latch circuits at later stages are further provided respectively in correspondence with n-bit latch circuits at previous stages holding output of an n-bit counter. The n-bit latch circuit at the later stage holds a digital pixel signal outputted from the n-bit latch circuit at the previous stage. The digital pixel signals held at the respective n-bit latch circuits at the later stages are sequentially shifted to one end side to be thereby taken out.
In the case of this document, a CDS (Correlated Double Sampling) circuit is further provided at a stage before each A/D converter. The CDS circuit is a circuit for reducing read noise and typically used in CCDs (see, for example, Japanese Unexamined Patent Publication No. 2007-282204).
The CDS circuit described in the above document performs noise cancellation on an analog pixel signal, but a technology of performing noise cancellation on a digital pixel signal obtained through A/D (Analog-to-Digital) conversion in the same manner is disclosed in Japanese Unexamined Patent Publication No. 2006-25189.
More specifically, with the image sensor described in this document, A/D conversion is performed by the A/D converter on each of a signal level and a reset level outputted from each pixel. The signal level obtained through the A/D conversion is stored into a first register, and the reset level obtained through the A/D conversion is stored into a second register. An adder obtains a difference between the level signals respectively stored in the first and second registers. With this configuration, offset variation of the A/D converter is cancelled, thus providing an advantage that variable noise of a column circuit causing vertical line noise is cancelled.